The present invention relates to a digital processing circuit, and more particularly to a digital circuit with a multiplication function making use of Booth's algorithm.
Owing to developments in large scale integrated circuit (LSI) techniques, it has become possible to digitally process signals (information) which have been heretofore processed in an analog manne Recently, LSI circuits have been used to process complex scientific calculations. One of the important functions in such type of digital processing circuits is a multiplication function. Moreover, in such signal processing, the multiplier circuit is often required to operate at high speed. Accordingly, research and development for a high speed multiplication algorithm has been carried out actively. The multiplication operation usually requires a process for producing partial products, a process for accumulating the produced partial products and a sign process. In order to achieve high speed operation, how these processes are executed and how skillfully they are combined is a major problem.
In general, a simple algorithm is employed. More specifically, in the case of multiplying a multiplicand X by a multiplier Y, partial products equal to the number of bits in the multiplier Y are produced by executing multiplications of the multiplicand X by the respective bits in the multiplier Y, and they are added together to obtain the results. However, in this algorithm, N partial products are produced for an N-bit multiplier Y, and N addition operations are required to obtain the result. A correction circuit for sign processing is also necessitated. Therefore, a great many hardware elements have to be included in the LSI device of this algorithm. As a consequence, it is not so valuable for practical purposes.
Among the other known multiplication algorithms, Booth's algorithm is useful. This is an algorithm in which a multiplier and a multiplicand represented in a complement form are multiplied by each other. According to this algorithm, the number of partial products is reduced by one-half with respect to the above-described simple algorithm (N/2), and sign processing is executed simultaneously in the process for producing partial products, this being favorable for high-speed processing. However, even though the number of partial products is reduced, hardware for executing Booth's algorithm becomes very complex. Especially, many circuit elements are required for producing partial products and for adding the produced partial products. Furthermore, the combination of these circuit elements is complex and hence the manufacture of an LSI circuit is difficult using Booth's algorithm.
Still further, in the case where the multiplier circuit of Booth's algorithm is used in a relatively low frequency band as in the case where it is used in speech synthesis, timing control for the circuit is difficult because of its high speed processing. For such multiplication processing of low frequency signals, it is more desirable to reduce the number of circuit elements rather than to realize high speed processing. In other words, a multiplier circuit matched to the operation speed of a low frequency signal processing circuit is required. Especially since a multiplier circuit is used for a digital filter section in a speech synthesizer system, timing control thereof is extremely important. Accordingly, even if a multiplication result is obtained through high-speed processing, delay circuits, latch circuits and the like must be added to the output stage of the multiplier circuit for the purpose of attaining synchronization with the other speech synthesizer circuits, so that more and more hardware circuit elements become necessary. It is desirable to provide a circuit design for performing multiplication according to Booth's algorithm.